The present invention may relate to co-pending application Ser. No. 10/011,936, filed concurrently, which is hereby incorporated by reference in its entirety.
The present invention relates to a method and/or architecture for interfacing fixed circuitry blocks to programmable logic blocks generally and, more particularly, to an architecture and/or method for implementing a set of configurable interface tiles that may be configured to interface fixed circuitry blocks to programmable logic blocks without modifying the fixed circuitry blocks or the programmable logic blocks.
As programmable logic devices are migrated to more advanced technologies, the integration of fixed function blocks (called cores) onto the same device (or in the same package) as programmable logic may become commonplace. The fixed function blocks are different than programmable logic in that the fixed function cores are designed to perform a specific function and are not programmable. However, the fixed function cores can be significantly faster and consume a smaller area than the same function implemented using programmable logic. In the past, the fixed circuitry blocks have been relatively small, such as memory blocks or multiplier blocks. However, in order to provide the performance demanded by programmable logic device customers, larger and more capable fixed function cores may be needed.
Existing programmable logic devices (PLDs) with embedded fixed function cores (FFCs) rely on ad-hoc techniques to connect the FFC to a programmable logic core (PLC). Typically, interface circuitry is embedded in either the fixed function cores or the programmable logic core. As an example, U.S. Pat. No. 6,064,599 describes a fixed memory array that can be embedded into a programmable logic device. The interface circuitry, as well as dedicated connections used to interconnect neighboring memory arrays is described as part of the memory arrays themselves. In another example, U.S. Pat. No. 6,204,689 describes input/output blocks, where the interconnect between the input/output blocks and the programmable logic is embedded within the programmable logic.
The conventional methods of interfacing FFCs with PLCs involve including the interface circuitry as part of either the fixed function core or the programmable logic core. While including the interface circuitry as part of the FFC is acceptable for very small FFCs (such as memories), implementing the interface circuitry as part of the FFC is not feasible for large FFCs. Often, the FFCs were originally designed and sold as stand-alone chips. Including interface circuitry within the stand alone cores can require a significant redesign effort. Similarly, including the interface circuitry in the PLC can require a redesign of the PLC every time a new fixed-function core is to be integrated. Typically, a family of hybrid devices can contain members that differ in the amount of programmable logic on the chip. Using the conventional ad-hoc interconnection techniques, the interconnect needs to be redesigned for each family member. Redesigning each family member can be unfeasible (cost prohibitive).
It would be desirable to have a structured method and/or architecture for integrating fixed-function and programmable logic cores that does not require the modification of either core.
The present invention concerns an apparatus comprising one or more configurable interface tiles. The configurable interface tiles may be configured to communicate one or more signals between a programmable logic core and a fixed function core. The one or more configurable interface tiles, the programmable logic core and the fixed function core may be integrated on a single chip.
The objects, features and, advantages of the present invention include providing configurable interface tiling that may (i) provide a set of configurable interface tiles (CITs) that may be used to interconnect a fixed function core and a programmable logic core on an integrated circuit, (ii) provide a method for constructing an integrated circuit containing one or more fixed function cores, one or more programmable logic cores, and one or more configurable interface tiles, and/or (iii) allow the coupling of fixed function cores and programmable logic cores on an integrated circuit without the cores being modified.